High Performance , Point - to - Point , Transmission Line

Inter-chip signaling latency and bandwidth can be key factors limiting the performance of large VLSI systems. We present a high performance, transmission line signaling scheme for point-to-point communications between VLSI components. In particular , we detail circuitry which allows a pad driver to sense the voltage level on the attached pad during signaling and adjust the drive impedance to match the external transmission line impedance. This allows clean, reeection-free signaling despite the wide range of variations common in IC device processing and interconnect fabrication. Further, we show how similar techniques can be used to adjust the arrival time of signals to allow high signal-ing bandwidth despite variations in interconnect delays. This scheme employed for high performance sig-naling is a speciic embodiment of a more general technique. Conventional electronic systems must accommodate a range of system characteristics (e.g. delay, voltage, impedance). As a result, circuit designers traditionally build large operating margins into their circuits to guarantee proper operation across all possible ranges of these characteristics. These margins are generally added at the expense of performance. The alternative scheme exempliied here is to sample these system characteristics in the device's nal operating environment and use this feedback to tune system operation around the observed characteristics. This tuning operation reduces the range of characteristics Acknowledgments:dation Graduate Fellowship. Any opinions, ndings, conclusions or recommendations expressed in this publication are those of the author and do not necessarily reeect the views of the National Science Foundation. the system must accommodate, allowing increased performance. We brieey contrast this sampled, system-level feedback with the more conventional, ne-grained feedback employed on ICs (e.g. PLLs).